The present invention generally relates to a bipolar-complementary metal oxide semiconductor inverter.
As is well known, a bipolar transistor has a driving capability greater than that of a complementary metal oxide semiconductor inverter (hereafter simply referred to as a CMOS inverter). Therefore, a bipolar transistor can charge up a load quickly, compared to a CMOS inverter. From this viewpoint, recently, there has been considerable activity in the development of a bipolar-CMOS inverter (hereafter simply referred to as a Bi-CMOS inverter) obtained by combining a bipolar transistor and a CMOS transistor. The CMOS inverter of the Bi-CMOS inverter performs a NOT operation for an input signal, and the bipolar transistor thereof drives a load coupled therewith in response to an output voltage of the CMOS inverter. The Bi-CMOS inverter contributes to an increased operational speed of a random access memory (RAM). Such Bi-CMOS inverters are disclosed in the Japanese Laid-Open Patent Application Nos. 141128/1982, 212827/1982 and 80929/1983, for example.
However, the conventional Bi-CMOS inverters have the following disadvantages. That is, when the input voltage is switched from a low level to a high level, the output voltage of the CMOS inverter may fall more quickly than the output voltage of the Bi-CMOS inverter which is applied to the load. Therefore, the p-n junction formed between the base and emitter of the bipolar transistor becomes biased in the reverse direction. As a result, a breakdown may be caused at the base-emitter junction.
The above problem can be overcome by making the output voltage of the CMOS inverter fall more slowly than the output voltage applied to the load. However, this causes an increased through current which passes through the bipolar transistor. The increased through current may introduce noise and causes an increased power consumption of the Bi-CMOS inverter.